Dynamic random access memories (DRAMs) are typically accessed in two phases. First, an address-specified page of data is transferred from a row of DRAM storage cells to a bank of sense amplifiers in a row activation operation. Thereafter, one or more column read or write operations are executed to retrieve or overwrite address-specified fractions (columns) of the page of data within the sense amplifier bank, thus reading or writing column data within the open page.
Row activation tends to be particularly time consuming, as low-amplitude signals stored within individual storage cells are sensed via long, high-capacitance bit lines. To mitigate this timing bottleneck, DRAMs have traditionally been architected with relatively high row to column ratios (e.g., 64:1 or 128:1) to increase the likelihood that back-to-back memory accesses will “hit” the same open page (i.e., exploiting spatial/temporal locality), and thus enable multiple relatively low-latency column operations per row activation. Unfortunately, the power expended to activate a given storage row is largely wasted as the vast majority of the data transferred to the sense amplifiers during row activation is untouched in ensuing column operations.